I Architectural Design for Address Interpretation in a Laboratory Address Recognition Unit ( LAR U )

The system architecture used for address interpretation in the CEDAR LARU is defined. Gray level address block images are input to the system and ZIP+4 Codes are output. The objective of the CEDAR address interpretation unit (AIU) design is to provide a platform that maximizes system throughput to allow for large-scale testing of algorithmic improvements in a laboratory environment. Thus, the time to put code developed by algorithm researchers into a testable prototype is minimized. A secone. dary objective is to build a system that has the capability to reach real-time processing rates (13 mailpieces per second). This paper outlines the basic architecture of the CEDAR AIU. Specialized image processing is performed on custom-designed hardware. This includes the reduction of image data to symbolic form, i.e., a serial representation of the contours of an address block image. All the subsequent processing of the address is performed on a bank of general purpose processors. An implementation that uses a commercially available multiprocessor board running a variant of the Unix operating system is described. This allows algorithm developers to directly compile code into the AID test environment from development workstations. The multiprocessor also supports up to 512 megabytes of memory (DRAM) that is used to store the nation'~vide ZIP+4 and DSF files. 1313 USPS Advanced Technology Conference, Washington, D.C., Nov. 30 Dec. 2, 1992